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16.10.2020
Martin Pagel

The Paper "Scotch: Generating FPGA-Accelerators for Sketching at Line Rate" was Accepted for Publication in PVLDB Vol. 14

"Scotch: Generating FPGA-Accelerators for Sketching at Line Rate". Martin Kiefer, Ilias Poulakis, Sebastian Breß, Volker Markl . To be Published in Proceedings of the VLDB Endowment (PVLDB), Vol. 14

Abstract:
Sketching algorithms are a powerful tool for single-pass data summarization. Their numerous applications include approximate query processing, machine learning, and large-scale network monitoring. In the presence of high-bandwidth interconnects or in-memory data, the throughput of summary maintenance over input data becomes the bottleneck. While FPGAs have shown admirable throughput and energy-efficiency for data processing tasks, developing FPGA accelerators requires a sophisticated hardware design and expensive manual tuning by an expert. In this paper, we propose Scotch, a novel system for accelerating sketch maintenance using the custom FPGA hardware. Scotch provides a domain-specific language for the user-friendly, high-level definition of a broad class of sketching algorithms. A code generator performs the heavy-lifting of hardware description, while an auto-tuning algorithm tunes the summary size. Our evaluation shows that FPGA accelerators generated by Scotch outperform CPU- and GPU-based sketching by up to two orders of magnitude in terms of throughput and up to one order of magnitude in terms of energy efficiency.

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